Introduction to Electronics

Introduction to Diodes

The Ideal Diode
 Terminal Characteristics of Junction Diode
 Modeling the Diode Forward Characteristic
 Operation in the Reverse Breakdown Region
 Physical Operation of Diodes
 Demonstration with CppSimulator

MOS Field-Effect Transistors (MOSFETs)

Device Structure and Physical Operation
 Current-Voltage Characteristics
 MOSFET Circuits at DC
 The MOSFET as an Amplifier and as a Switch
 Biasing in MOS Amplifier Circuits
 Small-Signal Operation and Models
 Single-Stage MOS Amplifiers
 The CMOS Digital Logic Inverter
 Demonstration with CppSimulator

Asic Design Flow

Introduction
 Specification
 RTL Coding
 Test Bench and Simulation
 Synthesis
 Prelayout Timing Analysis
 APR
 Back Annotation
 Post layout Timing Analysis
 Logic Verification

Verilog Coding

Introduction to Basic Verilog Concepts
 Comments
 Numbers
 Verilog Data Type
 Signal Strength
 Verilog Gate-Level Primitives
 User-Defined Primitives
 Concurrent and Sequential Statements
 Demonstration by using Verilator Integrated with
GTKWave

Coding Style

Naming Convention
 Design Partitioning
 Clock
 Reset
 Timing Loop
 Blocking and Nonblocking Statement
 Sensitivity List
 Verilog Operators
 Latch Inference
 Memory Array
 State Machine Design
 Demonstration by using Verilator Integrated with
GTKWave

Design Example of Programmable Time

 Programmable Timer Design Specification
 Microarchitecture Definition for Programmable Timer
 Flow Diagram Definition for Programmable Timer
 Verilog Code for Programmable Timer
 Synthesizable Verilog Code for Programmable Timer

Design Example of Programmable Logic Block for Peripheral Interface

 Programmable Logic Block for Peripheral Interface
Design Specification
 Mode of Operation for Programmable Logic Block for
Peripheral Interface
 Microarchitecture Definition for Programmable
Peripheral Interface
 Flow Diagram Definition for Programmable Peripheral
Interface
 Synthesizable Verilog Code for Programmable
Peripheral Interface
 Simulation for Programmable Peripheral Interface
Design
 Demonstration by using Verilator Integrated with
GTKWave

SystemVerilog Literal Values and Data Types

Predefined Gates
 Structural Modeling
 SystemVerilog Format Specifier
 Multi-bit Constants and Concatenation
 Literals
 Data Types
 Demonstration by using Verilator Integrated with
GTKWave

Combinational Design Using SystemVerilog

Role of always_comb Procedural Block
 Nested if-else and Priority Logic
 Parameter and Its Use in Design
 Conditional Operator and Use to Infer the Mux Logic
 Decoders

Sequential Design Using SystemVerilog

Intentional Latches Using always_latch
 PIPO Register Using always_ff
 Use Asynchronous Reset
Up-Down Counter
Shift Register
 Ring Counter
 Johnson Counter
 Implement RTL for Clocked Arithmetic Unit
 Implement RTL for Clocked Logic Unit

Design of Convolutional Neural Network Based on Verilog

Introduction to ANN
 Convolutional neural networks
 CNN Accelerator Design
 Experimenta

Introduction

Introduction
 Nanometer Designs .
 What is Static Timing Analysis?
 Why Static Timing Analysis?
 Design Flow
 STA at Different Design Phases
 Limitations of Static Timing Analysis
 Power Considerations
 Reliability Considerations

STA Concepts

CMOS Logic Design
 Modeling of CMOS Cells
 Switching Waveform
 Propagation Delay
 Slew of a Waveform
 Skew between Signals
 Timing Arcs and Unateness
 Min and Max Timing Paths
 Clock Domains
 Operating Conditions

Standard Cell Library

Pin Capacitance
 Timing Modeling
 Timing Models – Combinational Cells
 Timing Models – Sequential Cells
State-Dependent Models
 Interface Timing Model for a Black Box
 Advanced Timing Modeling
 Power Dissipation Modeling
 Other Attributes in Cell Library
 Characterization and Operating Conditions

Interconnect Parasitics

RLC for Interconnect
 Wireload Models
 Representation of Extracted Parasitics
 Representing Coupling Capacitances
 Hierarchical Methodology
 Reducing Parasitics for Critical Nets

Delay Calculation

Overview
 Cell Delay using Effective Capacitance
 Interconnect Delay
 Slew Merging
 Different Slew Thresholds
 Different Voltage Domains
 Path Delay Calculation
 Slack Calculation

Crosstalk and Noise

Crosstalk Glitch Analysis.
 Crosstalk Delay Analysis .
 Timing Verification Using Crosstalk Delay
 Computational Complexity
 Noise Avoidance Techniques

Configuring the STA Environment

What is the STA Environment? .
 Specifying Clocks
 Generated Clocks
 Constraining Input Paths
 Constraining Output Paths
 Timing Path Groups
 Modeling of External Attributes
 Design Rule Checks
 Virtual Clocks
 Refining the Timing Analysis
 Point-to-Point Specification
 Path Segmentation

Timing Verification

Setup Timing Check
 Hold Timing Check
 Multicycle Paths
 False Paths
 Half-Cycle Paths
 Removal Timing Check
 Recovery Timing Check
 Timing across Clock Domains
 Examples
 Multiple Clocks

Interface Analysis

IO Interfaces
 SRAM Interface
 DDR SDRAM Interface
 Interface to a Video DAC

Robust Verification

On-Chip Variations
 Time Borrowing
 Data to Data Checks
 Non-Sequential Checks
 Clock Gating Checks
 Power Management
 Backannotation
 Sign-off Methodology
 Statistical Static Timing Analysis
 Paths Failing Timing?
 Validating Timing Constraints