Interconnect Parasitics

Course Content
Micro Electronics
0/3
Introduction to Electronics
Introduction to Diodes
MOS Field-Effect Transistors (MOSFETs)
Verilog-HDL
0/5
Asic Design Flow
Verilog Coding
Coding Style
Design Example of Programmable Time
Design Example of Programmable Logic Block for Peripheral Interface
System Verilog
0/3
SystemVerilog Literal Values and Data Types
Combinational Design Using SystemVerilog
Sequential Design Using SystemVerilog
Verilog Neural Network
0/1
Design of Convolutional Neural Network Based on Verilog
STA (Qflow Design)
0/10
Introduction
STA Concepts
Standard Cell Library
Interconnect Parasitics
Delay Calculation
Crosstalk and Noise
Configuring the STA Environment
Timing Verification
Interface Analysis
Robust Verification
VLSI WITH AI & ML
About Lesson

RLC for Interconnect
 Wireload Models
 Representation of Extracted Parasitics
 Representing Coupling Capacitances
 Hierarchical Methodology
 Reducing Parasitics for Critical Nets

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